Local Search For Final Placement in VLSI-design: DIKU-rapport 01/01

A new heuristic is presented for the general cell placement
problem where the objective is to minimize total bounding box
netlength. The heuristic is based on the Guided Local Search
(GLS) metaheuristic. GLS modifies the objective function in a
constructive way to escape local minima. Previous attempts to
use local search on final (or detailed) placement problems have
often failed as the neighborhood quickly becomes too excessive for large circuits. Nevertheless, by combining GLS with
Fast Local Search it is possible to focus the search on appropriate sub-neighborhoods, thus reducing the time complexity
considerably.
Comprehensive computational experiments with the developed algorithm are reported on small, medium and large industrial circuits, and for standard cell and general cell variants
of the problem. The experiments demonstrate that the developed algorithm is able to improve the estimated routing length
of large-sized general cell layouts with as much as 20 percent.
The general nature of the proposed method makes it easy
to incorporate other goals, such as routability and timing constraints, into the objective function. Current layout algorithms
use a feedback approach in which a placement is evaluated
by performing (partial) routing and timing analysis; the output
of this analysis is then used to construct an improved placement. This iterative nature of the design process calls for
placement algorithms that take an existing placement and construct an improved placement that resembles the original one,
but in which the information from the routing/timing analysis
is taken into account